1. Field of the Invention
The present invention relates to semiconductor packages and methods of fabricating the same, and more particularly to a semiconductor package having a semiconductor chip with high inputs/outputs and a method of fabricating the same.
2. Description of the Prior Art
As the technology for developing electronic products is steadily growing, electronic products have now moved to multi-functionality and high functionality. The semiconductor packaging technology has been widely used nowadays includes chip scale package (CSP), Direct Chip Attached (DCA), Multi Chip Module (MCM), and 3D-IC stacking technology.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1, wherein a through silicon interposer (TSI) 10 is formed between the substrate 18 and a semiconductor chip 11. The TSI 10 has a plurality of through-silicon vias (TSVs) 100 and a redistribution layer (RDL) 15 formed on the through-silicon vias (TSVs) 100, allowing the redistribution layer 15 to be electrically connected through the plurality of conductive elements 14 with solder pads 180 on the substrate 18. The spacing distance between the solder pads 180 is greater than that of the conductive elements 14. The conductive elements 14 are covered by an adhesive material, and the electrode pads 110 of the semiconductor chip 11 are electrically connected to the through-silicon vias (TSV) 100 through a plurality of solder bumps 13. An adhesive material is then applied to cover the solder bumps 13.
If the semiconductor chip 11 is directly attached to the substrate 18, since the heat expansion coefficient difference between the smaller semiconductor chip and circuit substrate is rather large, it is difficult to establish a good bonding between the solder bumps 13 on the periphery of the chip 11 and the corresponding solder pads 180, causing the solder bumps 13 to be easily detached from the substrate 18. In addition, due to problems associated with thermal stress and warpage as a result of mismatch of heat expansion coefficient between semiconductor chip and substrate, the reliability between the semiconductor chip and the substrate is decreased causing frequent failures in reliability test.
Accordingly, by providing an interposer 10 made of silicon in the fabricating process of the semiconductor substrate, since the material thereof is similar to the semiconductor chip 11, the conventional problems can be solved.
In addition, through the design of the interposer 10, the disposing area of the semiconductor package can be further reduced in comparison with a flip-chip package. Generally, in the flip-chip package, the minimum line width or space of conductive traces is 12/12 μm. Therefore, the disposing area must increase to meet the requirement for semiconductor chip with high inputs/outputs (I/O). Providing interposer 10 in the fabricating process, it is possible to have line width and space under 3/3 μm, allowing the semiconductor chip 11 to be electrically connected with the substrate 18 through the interposer without the need to increase the area of the substrate 18.
In addition, in the interposer 10 design, due to the property of fine trace lines, and small line width, the distance for electricity transmission is relatively shorter. Therefore, the overall electricity transmission speed of the semiconductor chip 11 on the interposer is faster in comparison with the flip-chip package.
However, the disadvantage for fabricating the conventional semiconductor package 1 is the reflow process performed to solder the interposer 10 on the substrate 18. This creates thermal stress to be focused on the interface between the conductive element 14 and conductive vias, as shown as the thermal concentrated area K′ in FIG. 1, causing the interface between the conductive elements 14 and conductive vias 100 (or the redistribution layer 15) to be cracked, thereby undesirably reducing the reliability and yield of the final product.
Therefore, there is an urgent need in solving the foregoing problems.